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complete 10 - bit and 12 - bit, 25 mhz ccd signal processor s data sheet ad9943/ad9944 features 25 msps correlated double sampler (cds) 6 db to 40 db 10 -b it variable gain amplifier (vga) low noise optical black clamp circuit preblanking f unction 10 -b it ( ad9943 ), 12 - bit ( ad9944 ) 25 msps a/d c onverter no missing codes guaranteed 3- wire serial digital interface 3 v single - supply ope ration space -s aving 32 -l ead 5 mm 5 mm lfcsp p ackage applications digital still cameras digital video camcorders pc c ameras portable ccd imaging devices cctv c ameras general description the ad9943 / ad9944 are complete analog signal processors for ccd applications. they feature a 25 mhz single - channel architecture designed to sample and condition the outputs of interlaced and pr ogressive scan area ccd arrays. the signal chain for the ad9943 / ad9944 consists of a correlated double sampler (cds), a digitally controlled variable gain amplifier (vga), and a black level clamp. the ad9943 offers 10 - bit adc resolution, while the ad9944 contains a true 12 - bit adc. the internal registers are programmed through a 3- wire serial digital interface. programmable features include gain adjustment, black level adjustment, input clock pol arity, and power - down modes. the ad9943 / ad9944 operate from a single 3 v power supply, typically dissipate 79 mw, and are pack aged in space - saving 32 - lead lfcsp packages. functional block dia gram f igure 1 . functional block diagram dataclk shd shp band gap reference dout ccdin pblk reft refb internal timing 6db?40db avdd dvdd dvss avss drvdd drvss 10 digital interface sdata sck sl clpob 10/12 cds vga clp ad9943/ad9944 control registers 10-/12-bit adc 02905-b-001 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any paten t or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. o ne technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2004C 2014 analog devices, inc. all rights reserved. technical support www.analog.com
ad9943/ad9944 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 general specifications ................................................................. 3 digital specifications ................................................................... 3 ad9943 system specifications ................................................... 3 ad9944 system specifications ................................................... 4 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 ter mi nolo g y ...................................................................................... 9 equivalent input circuits .............................................................. 10 typical performance characteristics ........................................... 11 internal register map .................................................................... 12 serial interface ................................................................................ 13 circuit description and operation .............................................. 14 dc restore .................................................................................. 14 correlated double sampler ...................................................... 14 optical black clamp .................................................................. 14 a/d converter ............................................................................ 15 variable gain amplifier ............................................................ 15 ccd mode timing ........................................................................ 16 applications information .............................................................. 17 internal power - on reset circuitry .......................................... 18 grounding and decoupling recommendations .................... 18 outline dimensions ....................................................................... 19 ordering guide ............................................................................... 19 revision history 3 /14 rev. b to rev. c added exposed pad notation, figure 2 and table 6 ................... 7 added exposed pad notation, figure 3 and table 7 ................... 8 changes to figure 17 ...................................................................... 17 changes to figure 18 ...................................................................... 18 updated outline dimensions ....................................................... 19 changes to ordering guide .......................................................... 19 5/04 data sheet changed from rev. a to rev. b updated format .................................................................. universal updated outline dimensions ....................................................... 20 changes to ordering guide .......................................................... 20 5/03 data sheet changed from rev. 0 to rev. a added ad9944 ................................................................... universal chan ges to features section ............................................................ 1 updated ordering g uide ................................................................. 5 replaced tpc 3 ................................................................................. 9 added figure 12 .............................................................................. 15 updated outline dimensions ....................................................... 16 rev. c | page 2 of 20
data sheet ad9943/ad9944 specifications general specifications t min to t max , avdd = dvdd = drvdd = 3 v, f samp = 25 mhz, unless otherwise noted. table 1. parameter min typ max unit temperature range operating ?20 +85 c storage ?65 +150 c power supply voltage analog, digital, digital driver 2.7 3.6 v power consumption normal operation 79 mw power - down mode 150 w maximum clock rate 25 mhz d igital s pecifications drvdd = dvdd = 2.7 v, c l = 20 pf, unless otherwise noted. parameter symbol min typ max unit logic inputs high level input voltage v ih 2.1 v low level input voltage v il 0.6 v high level input current i ih 10 a low level input current i il 10 a input capacitance c in 10 pf logic outputs high level output voltage, i oh = 2 ma v oh 2.2 v low level output voltage, i ol = 2 ma v ol 0.5 v ad9943 s ystem s pecifications t min to t max , avdd = dvdd = drvdd = 3 v, f samp = 25 mhz, unless otherwise noted. table 2. parameter min typ max unit conditions cds maximum input range before saturation 1 1.0 v p -p allowable ccd reset transient 1 500 mv see input waveform in footnote . maximum ccd black pixel amplitude 1 100 mv variable gain amplifier (vga) gain control resolution 1024 steps gain monotonicity guaranteed gain range minimum gain 5.3 db see figure 13 for vga gain curve. maximum gain 40 41.5 db see variable gain amplifier section for vga gain equation . black level clamp clamp level resolution 256 steps clamp level measured at adc output . minimum clamp level 0 lsb maximum clamp level 63.75 lsb rev. c | page 3 of 20
ad9943/ad9944 data sheet parameter min typ max unit conditions a/d converter resolution 10 bits differential nonlinearity (dnl) 0.3 lsb no missing codes guaranteed data output coding straight b inary full - scale input voltage 2.0 v voltage reference reference top voltage (reft) 2.0 v reference bottom voltage (refb) 1.0 v system performance specifications include entire signal chain . gain range low gain (vga code = 0) 5.3 db maximum gain (vga code = 1023) 40 41.5 db gain accuracy 1 db peak nonlinearity 500 mv input signal 0.1 % 12 db gain applied . total output noise 0.3 lsb rms ac grounded input, 6 db gain applied . power supply rejection (psr) 50 db measured with step change on supply . 1 input signal characteristics defined as follows: ad9944 s ystem s pecifications t min to t max , avdd = dvdd = drvdd = 3 v, f samp = 25 mhz, unless otherwise noted. table 3. parameter min typ max unit conditions cds maximum input range before saturation 1 1.0 v p -p allowable ccd reset transient 1 500 mv see input waveform in footnote . maximum ccd black pixel amplitude 1 100 mv variable gain amplifier (vga) gain control resolution 1024 steps gain monotonicity guaranteed gain range minimum gain 5.3 db see figure 13 for vga gain curve . maximum gain 40 41.5 db see variable gain amplifier section for vga gain equation . black level clamp clamp level resolution 256 steps clamp level measured at adc output . minimum clamp level 0 lsb maximum clamp level 255 lsb a/d converter resolution 12 bits differential nonlinearity (dnl) 0.4 lsb no missing codes guaranteed data output coding straight b inary full - scale input voltage 2.0 v 100mv typ optical black pixel 500mv typ reset transient 1v typ input signal range 02905-b-002 rev. c | page 4 of 20
data sheet ad9943/ad9944 parameter min typ max unit conditions voltage reference reference top voltage (reft) 2.0 v reference bottom voltage (refb) 1.0 v system performance specifications include entire signal chain . gain range low gain (vga code = 0) 5.3 db maximum gain (vga code = 1023) 40 41.5 db gain accuracy 1 db peak nonlinearity 500 mv input signal 0.1 % 12 db gain applied . total output noise 0.9 lsb rms ac grounded input, 6 db gain applied . power supply rejection (psr) 50 db measured with step change on supply . 1 input signal characteristics defined as follows: t iming specifications c l = 20 pf, f samp = 25 mhz. see ccd -m ode t iming in figure 14 and figure 15, and s erial timing in figure 10 and figure 11 . table 4. parameter symbol min typ max unit sample clocks dataclk, shp, shd clock period t conv 40 ns dataclk high/low pulse w idth t adc 16 20 ns shp pulse w idth t shp 10 ns shd pulse w idth t shd 10 ns clpob pulse w idth 1 t cob 2 20 pixels shp rising edge to shd falling edge t s1 10 ns shp rising edge to shd rising edge t s2 16 20 ns internal clock delay t id 3.0 ns data outputs output delay t od 9.5 ns pipeline delay 9 cycles serial interface maximum sck frequency f sclk 10 mhz sl to sck setup time t ls 10 ns sck to sl hold time t lh 10 ns sdata valid to sck rising edge set up t ds 10 ns sck falling edge to sdata valid hold t dh 10 ns 1 minimum clpob pulse width is for functional operation only. wider typical pulses are recommended to achieve low noise clamp p erformance. 100mv typ optical black pixel 500mv typ reset transient 1v typ input signal range 02905-b-002 rev. c | page 5 of 20
ad9943/ad9944 data sheet absolute maximum rat ings table 5. parameter (with respect to) min max unit avdd ( avss ) ? 0.3 +3.9 v dvdd ( dvss ) ? 0.3 +3.9 v drvdd ( drvss ) ? 0.3 +3.9 v digital outputs ( drvss ) ? 0.3 drvdd + 0.3 v shp, shd, dataclk ( dvss ) ? 0.3 dvdd + 0.3 v clpob, pblk ( dvss ) ? 0.3 dvdd + 0.3 v sck, sl, sdata dvss (avss) ? 0.3 dvdd + 0.3 v reft, refb, ccdin ? 0.3 avdd + 0.3 v junction temperature 150 c lead temperature (10 sec) 300 c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance the t hermal r esistance of a 32 - l ead lfcsp package ( with the exposed bottom pad soldered to the board gnd) is j a = 27.7 c / w. esd caution rev. c | page 6 of 20
data sheet ad9943/ad9944 pin configuration and function descripti ons figure 2. ad9943 pin configuration table 6. ad9943 pin function descriptions pin no. mnemonic type 1 description 1 to 10 d0 to d9 do digital data outputs. 11 drvdd p digital output driver supply. 12 drvss p digital output driver ground. 13 dvdd p digital supply. 14 dataclk di digital data output latch clock. 15 dvss p digital supply ground. 16 pblk di preblanking clock input. 17 clpob di black level clamp clock input. 18 shp di cds sampling clock for ccd reference level. 19 shd di cds sampling clock for ccd data level. 20 avdd p analog supply. 21 avss p analog ground. 22 ccdin ai analog input for ccd signal. 23 reft ao a/d converter top reference voltage decoupling. 24 refb ao a/d converter bottom reference voltage decoupling. 25 sl di serial digital interface load pulse. 26 sdata di serial digital interface data input. 27 sck di serial digital interface clock input. 28 to 30 nc nc internally p ulled d own. float or connect to gnd. 31 to 32 nc nc internally n ot c onnected. epad exposed pad. solder the exposed pad to the ground plane of the pcb. 1 type: ai = a nalog i nput, ao = a nalog o utput, di = d igital i nput, do = d igital o utput, p = p ower, and nc = n o c onnect. refb reft ccdin avss d0 d1 d2 nc 2 avdd shd shp clpob d8 d9 drvdd drvss dvdd dataclk dvss pblk d3 d4 d5 d6 d7 nc 2 nc 1 nc 1 nc 1 sck sdata sl 1 nc = no connec t . internal ly pulled down. flo a t or connect t o gnd. 2 nc = no connec t . internal ly not connected. notes 1. solder the exposed p ad t o the ground plane of the pcb. 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 ad9943 top view (not to scale) 02905-003 rev. c | page 7 of 20
ad9943/ad9944 data sheet figure 3 . ad9944 pin configuration table 7. ad9944 pin function descriptions pin no. mnemonic type 1 description 1 to 10 d2 to d11 do digital data outputs. 11 drvdd p digital output driver supply. 12 drvss p digital output driver ground. 13 dvdd p digital supply. 14 dataclk di digital data output latch clock. 15 dvss p digital supply ground. 16 pblk di preblanking clock input. 17 clpob di black level clamp clock input. 18 shp di cds sampling clock for ccd reference level. 19 shd di cds sampling clock for ccd data level. 20 avdd p analog supply. 21 avss p analog ground. 22 ccdin ai analog input for ccd signal. 23 reft ao a/d converter top reference voltage decoupling. 24 refb ao a/d converter bottom reference voltage decoupling. 25 sl di serial digital interface load pulse. 26 sdata di serial digital interface data input. 27 sck di serial digital interface clock input. 28 to 30 nc nc internally p ulled d own. float or connect to gnd. 31 d0 do digital data output. 32 d1 do digital data output. epad exposed pad. solder the exposed pad to the ground plane of the pcb. 1 type: ai = analog input, ao = analog output, di = digital input, do = digital output, p = p ower, and nc = n o c onnect . refb reft ccdin avss d2 d3 d4 d1 avdd shd shp clpob d10 d11 drvdd drvss dvdd dataclk dvss pblk d5 d6 d7 d8 d9 d0 nc nc nc sck sdata sl 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 ad9944 top view (not to scale) notes 1. nc = no connec t . internal ly pulled down. flo a t or connect t o gnd. 2. solder the exposed p ad t o the ground plane of the pcb. 02905-004 rev. c | page 8 of 20
data sheet ad9943/ad9944 terminology differential nonlinearity (dnl) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. therefore every code must have a finite width. no missing codes guaranteed to 10 - bit resolution indicates that all 1024 codes, respectively, must be present over all operating conditions. peak nonlinearity peak nonlinearity, a full - signal chain specification, refer s to the peak deviation of the output of the ad9943 / ad9944 from a true straight line. the point used as zero scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular output code to the true straight line. the error is then expressed as a percentage of the 2 v adc full - scale signal. the input signal is always appropriately gained up to fill the adcs full - scale range. total output noise the rms output noise is measured using histogram techniques. the standard deviation of the adc output cod es is calculated in lsb and represents the rms noise level of the total signal chain at the specified gain setting. the output noise can be converted to an equivalent voltage, using the relationship ( ) codes scale full adc n 2 lsb 1 = n is the bit resolution of t he adc. for example, 1 lsb of the ad9943 is 1.95 mv. power supply rejection (psr) the psr is measured with a step change applied to the supply pins. this represents a very high frequency dis turbance on the ad9943 / ad9944 s power supply. the psr specification is calculated from the change in the data outputs for a gi ven step change in the supply voltage. internal delay for shp/shd the internal delay (also called aperture delay) is the time delay that occurs from the time a sampling edge is applied to the ad9943 / ad9944 until the actual sample of the input signal is held. both shp and shd sample the input signal during the transitio n from low to high, so the internal delay is measured from each clocks rising edge to the instant the actual internal sample is taken. rev. c | page 9 of 20
ad9943/ad9944 data sheet equivalent input cir cuits figure 4 . digital inputs shp, shd, dataclk, clob, pblk, sck, sl figure 5 . data outputs figure 6 . ccdin (pin 22) 330? dvdd dvss input 02905-b-005 dvdd dvss drvss drvdd three- state data dout 02905-b-006 avdd avss avss 02095-b-007 60 ? rev. c | page 10 of 20
data sheet ad9943/ad9944 typical performance characteristics figure 7 . ad9943 / ad9944 power vs. sample rate figure 8 . ad9943 typical dnl performance figure 9 . ad9944 typical dnl performance sample rate (mhz) 100 50 25 15 power dissipation (mv) 10 80 20 90 70 60 v dd = 3.3v v dd = 3.0v v dd = 2.7v 40 02905-b-008 0 1000 400 200 600 800 0 ? 0.50 0.50 0.25 ? 0.25 02905-b-009 0.50 0.25 0 ? 0.25 ? 0.50 0 800 1600 2400 3200 4000 02905-b-010 rev. c | page 11 of 20
ad9943/ad9944 data sheet internal register ma p all register values default to 0x000 at power - up except clamp level, which defaults to 128 decimal ( ad9943 = 32 lsb clamp level, and ad9944 = 128 lsb clamp level). table 8. address bits register name a2 a1 a0 data bits function operation 0 0 0 d0 software reset (0 = n ormal o peration, 1 = reset all registers to default). d2, d1 power - down modes (00 = normal power, 01 = standby, 10 = total shutdown). d3 ob clamp disable (0 = clamp on, 1 = clamp off ). d5, d4 test mode. should always be set to 00. d6 pblk blanking level (0 = blank output to zero, 1 = blank to ob clamp level). d8, d7 test mode 1. should always be set to 00. d11 to d9 test mode 2. should always be set to 000. control 0 0 1 d0 shp/shd input polarity (0 = active low, 1 = active high). d1 dataclk input polarity (0 = active low, 1 = active high). d2 clpob input polarity (0 = active low, 1 = active high). d3 pblk input polarity (0 = active low, 1 = active high). d4 three - state data outputs (0 = outputs active, 1 = outputs three - stated). d5 data output latching (0 = latched by dataclk, 1 = latch is transparent). d6 data output coding (0 = binary output, 1 = gray code output). d11 to d7 test mode. should always be set to 00000. clamp level 0 1 0 d7 to d0 ob clamp level ( ad9943 : 0 = 0 lsb, 255 = 63.75 lsb, ad9944 : 0 = 0 lsb, 255 = 255 lsb). vga gain 0 1 1 d9 to d0 vga gain (0 = 6 db, 1023 = 40 db). rev. c | page 12 of 20
data sheet ad9943/ad9944 serial interface figure 10 . serial write operation figure 11 . continuous serial write operation to all registers t ls t lh sdata sck sl test bit a2 0 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 t ds t dh notes 1. sdata bits are internally latched on the rising edges of sck. 2. system update of loaded registers occurs on sl rising edge. 3. all 12 data bits d0 ? d11 must be written. if the register contains fewer than 12 bits, zeros should be used for the undefined bits. 4. test bit is for internal use only and must be set low. d11 02905-b-011 sdata a0 a1 a2 d0 d1 d2 d3 d4 d5 d10 d11 sck sl 0 notes 1. multiple sequential registers may be loaded continuously. 2. the first (lowest address) register address is written, followed by multiple 12-bit data-words. 3. the address automatically increments with each 12-bit data-word. (all 12 bits must be written.) 4. sl is held low until the last desired register has been loaded. 5. new data is updated at the next sl rising edge. d0 d1 d10 d11 d0 ... ... ... data for starting register address data for next register address d2 d1 ... ... 1 16 2 3 4 5 6 7 8 9 1 0 15 18 17 28 27 30 29 31 test bit 02905-b-012 rev. c | page 13 of 20
ad9943/ad9944 data sheet c ircuit d escription and o peration figure 12 . ccd mode block diagram the ad9943 / ad9944 signal processing chain is shown in figure 12 . each processing step is essential for achieving a high quality image from the raw ccd pixel data. dc restore to reduce the large dc offset of the ccd out put signal, a dc restore circuit is used with an external 0.1 f series coupling capacitor. this restores the dc level of the ccd signal to approximately 1.5 v, which is compatible with the 3 v single supply of the ad9943 / ad9944 . correlated double sa mpler the cds circuit samples each ccd pixel twice to extract video information and reject low frequency noise. the timing shown in figure 14 illustrates how the two cds clocks, shp and shd, are used, respectively, to sample the reference level and data level of the ccd signal. the ccd signal is sampled on the rising edges of shp an d shd. placement of these two clock signals is critical for achieving the best performance from the ccd. an internal shp/shd delay (t id ) of 3 ns is caused by internal propagation delays. optical black clamp the optical black clamp loop is used to remove r esidual offsets in the signal chain and to track low frequency variations in the ccds black level. during the optical black (shielded) pixel interval on each line, the adc output is compared with the fixed black level reference selected by the user in the clamp level register. the resulting error signal is filtered to reduce noise, and the correction value is applied to the adc input through a d/a converter. normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. if external digital clamping is used during the post processing, the optical black clamping for the ad9943 / ad9944 may be disabled using bit d3 in the operation register. refer to table 8 and figure 10 and figure 11. when the loop is disabled, the clamp level register may still be used to provide programmable offset ad justment. horizontal timing is shown in figure 15 . the clpob pulse should be placed during the ccds optical black pixels. it is recommended that the clpob pulse be use d during valid ccd dark pixels. the clpob pulse should be a minimum of 20 pixels wide to minimize clamp noise. shorter pulse widths may be used, but clamp noise may increase and the loops ability to track low frequency variations in the black level is red uced. 6db to 40db ccdin digital filtering clpob dc restore optical black clamp dout 1 0 - / 1 2 - b i t adc vga 8-bit dac clamp level register 8 vga gain register 10 cds internal v ref 2v full scale 10/12 0.1f 02905-b-013 rev. c | page 14 of 20
data sheet ad9943/ad9944 a/d converter the adc uses a 2 v input range. better noise performance results from using a larger adc full - scale range. the adc uses a pipelined architecture with a 2 v full - scale input for low noise performance. variable gain amplif ier the vga stage provides a gain range of 6 db to 40 db, programmable with 10 - bit resolution through the serial digital interface. the minimum gain of 6 db is needed to match a 1 v input signal with the adc full - scale range of 2 v. a plot of the vga gain curv e is shown in figure 13. ( ) ( ) db 3 . 5 db 035 . 0 db + = code vga gain vga fiue vga gain cue vga gain register mode 42 12 383 127 vga gain (db) 0 30 255 36 34 18 6 511 639 767 895 1023 02905-b-014 rev. c | page 15 of 20
ad9943/ad9944 data sheet ccd mode timing figure 1 4 . ccd mode timing figure 15 . typical ccd mode line clamp timing n n + 1 n + 2 n + 9 n + 10 t od t s1 t id t id n ? 10 n ? 9 n ? 8 n ? 1 n notes 1. recommended placement for dataclk rising edge is between the shd rising edge and next shp falling edge. 2. ccd signal is sampled at shp and shd rising edges. shp shd dataclk output data ccd signal t s2 t cp 02905-b-015 ccd signal effective pixels clpob o pt i c a l b l a c k pi xel s horizontal blanking dummy pixels effect ive pixe l s pblk notes 1. clpob will overwrite pblk. pblk will not affect clamp operation if overlapping with clpob. 2. pblk signal is optional. 3. digital output data will be all zeros during pblk. output data latency is nine dataclk cycles. output data effective pixel data o b pi xel d a t a d u mmy b l a c k ef f ec t i ve d a t a 02905-b-016 rev. c | page 16 of 20
data sheet ad9943/ad9944 applications information the ad9943 / ad9944 are complete analog front end (afe) products for digital still camera and camcorder applications. as shown in figure 12 , the ccd image (pixel) data is buffered and sent to the ad9943 / ad9944 analog input through a series inpu t capacitor. the ad9943 / ad9944 perform the dc restoration, cds, gain adjustment, black level correction, and analog - to - digital conversion. the ad9943 / ad9944 s digital output data is then processed by the image processing asic. the internal registers of the ad9943 / ad9944 used to control gain, offset level, and other functions are programmed by the asic or microprocessor throug h a 3 - wire serial digital interface. a system timing generator provides the clock signals for both the ccd and the afe. figure 16 . system applications diagram figure 17 . ad9943 recommended circuit configuration for ccd mode ccd ccdin bu ffer v out ad9943/ad9944 ad c out register data serial interface digital outputs digital image processing asic timing generator v-drive ccd timing cds/clamp timing 0.1 f 02905-b-017 24 refb 23 reft 22 ccdin 21 avss d0 1 d1 2 d2 3 nc 20 avdd 19 shd 18 shp 17 clpob d3 4 d4 5 d5 6 d6 7 d7 8 data outputs 10 d8 d9 9 10 3v driver supply 3v analog supply 3v analog supply drvdd drvss dvdd dataclk dvss pblk 12 13 14 15 16 5 clock inputs 3 serial interface ccdin 1.0f 1.0f 0.1f 0.1f 0.1f 0.1f nc = no connect 32 31 30 29 28 27 26 25 nc nc nc nc sck sdta sl 11 02905-018 ad9943 t op view (not to scale) rev. c | page 17 of 20
ad9943/ad9944 data sheet figure 18 . ad9944 recommended circuit c onfiguration for ccd mode internal power - on reset circuitry after power - on, the ad9943 / ad9944 automatically reset all internal registers and perform internal calibration procedures. this takes approximately 1 ms to complete. during this time, normal clock signals and serial write operations may occur. however, seria l register writes are ignored until the internal reset operation is completed. grounding and decoup ling recommendations as shown in figure 17 and f igure 18 , a single ground plane is recommended for the ad9943 / ad9944 . this ground plane should be as continuous as possible. this ensures that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. all decoupling capacitors sh ould be located as close as possible to the package pins. a single clean power supply is recommended for the ad9943 and ad9944 , but a separate digital driver supply may be used for drvdd (pin 11). drvdd should always be decoupled to drvss (pin 12), which should be connected to the analog ground plane. advantages of using a separate digital driver supply include using a lowe r voltage ( 2.7 v) to match levels with a 2.7 v asic, and reducing digital power dissipation and potential noise coupling. if the digital outputs must drive a load larger than 20 pf, buffering is the recommended method to reduce digital code transition noi se. alternatively, placing series resistors close to the digital output pins may also help reduce noise. note: the exposed pad on the bottom of the ad9943 / ad9944 should be soldered to the gnd plane of the printed circuit board. 24 refb 23 reft 22 ccdin 21 avss d2 1 d3 2 d0 d1 d4 3 20 avdd 19 shd 18 shp 17 clpob d5 4 d6 5 d7 6 d8 7 d9 8 data outputs 12 d10 d11 9 10 3v driver supply 3v analog supply 3v analog supply drvdd drvss dvdd dataclk dvss pblk 12 13 14 15 16 5 clock inputs 3 serial interface ccdin 1.0f 1.0f 0.1f 0.1f 0.1f 0.1f nc = no connect 32 31 30 29 28 27 26 25 nc nc nc sck sdta sl 11 02905-019 ad9944 t op view (not to scale) rev. c | page 18 of 20
data sheet ad9943/ad9944 outline dimensions figure 19 . 32- lead lead frame chip scale package [lfcsp _wq ] 5 mm 5 mm body , very very thin quad (cp - 32 -7) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9943kcpz ? ? ? ? compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bot t om view top view pin 1 indic at or 32 9 16 17 24 25 8 exposed pa d pin 1 indic at or 3.25 3.10 sq 2.95 sea ting plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min rev. c | page 19 of 20
ad9943/ad9944 data sheet notes ? 2004 C 2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02905 - 0 - 3/14(c) rev. c | page 20 of 20

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